The present invention relates generally to the integration of external circuitry into microelectronic circuitry, and, more particularly, to the fabrication and integration of applique circuits into microelectronic circuitry, and most particularly, to the fabrication and integration of applique capacitors into microelectronic circuitry.
Electronic circuits have in recent years become increasingly fast. A difficulty associated with increasing operating frequencies, especially in digital or coupled analog-digital applications, is that extremely high circuit switching speeds make for increased difficulties with induced electrical noise. A common problem is high frequency switching noise induced in an operating circuit having a relatively lower frequency of operation. An example is noise spikes induced at the input of an amplifier, or in the power supply of such an amplifier. Clearly it is of benefit to exclude such noise spikes from the active regions of the circuitry.
One way to address this problem is to use decoupling capacitors (sometimes also termed bypass or balancing capacitors). Such application, which is well known in the art, utilizes the frequency-variable impedance of a capacitor to separate the noise pulses from the desired signal. In the above example, a properly designed decoupling capacitor will present a very high impedance to the relatively low frequency desired signal, whereas it will appear nearly as a dead short to the relatively high frequencies associated with short-duration noise spikes. If such a decoupling capacitor is connected across the input of the amplifier, the desired signal will be able to reach the input of the amplifier, whereas the noise spikes will appear to be shorted to ground, and will not enter. Similarly, spikes coming into the amplifier via the power supply can be selectively shorted to ground, while the desired power input is not affected.
The closer such a decoupling capacitor is to the load, the more effective it is in eliminating or reducing any high-frequency noise which might affect the desired operation of the circuitry. Ideally in an integrated circuit chip, such a decoupling capacitor would be fabricated on the active integrated circuit chip itself. Such a decoupling capacitor, however, is very difficult to manufacture using existing techniques, and is thus more commonly attached at the circuit board. This approach, although useful in many circumstances, does not allow the designer to properly optimize the high- and low-frequency behaviors of the decoupling circuitry, nor does it allow for maximization of the protective decoupling effect by placing decoupling capacitors close to the load.
Integration of decoupling capacitors on an integrated circuit chip, however, has many difficulties and drawbacks. Direct integration of suitable decoupling capacitors using conventional silicon-based integrated circuit fabrication technology, for example, is impractical. The capacitance desired is typically in the 10-100 nanoFarad (nF) regime, and operating voltages are typically 5 volts. Using materials commonly available in integrated circuit fabrication (e.g., silicon nitride for use as the dielectric material), the capacitance of a single-layer capacitor capable of withstanding the operating voltage is about 1 nF per cm.sup.2. As multi-layer capacitors are quite difficult to fabricate using integrated circuit fabrication technology (especially those having many more than one active layer), it is clear that on the order of 100 cm.sup.2 of chip area would have to be dedicated to fabrication of single-layer decoupling capacitors to protect the power and signal inputs of even a rather simple integrated circuit. Such a solution is quite impractical. Similarly, although thin-film capacitors using materials having high dielectric constants (such as ferroelectric perovskites) can be made, the conditions encountered during their fabrication are generally incompatible with conventional integrated circuit fabrication.
Other approaches exist, such as including discrete decoupling capacitors within the package of the integrated circuit, or attached in some manner to the surface of the integrated circuit itself, but prior attempts in such directions have met with systemic difficulties which seriously limit or prevent their application. These approaches have centered on trying to mount ceramic chip decoupling capacitors on or near an integrated circuit at some point during processing. At least two types of difficulties appear, that of size incompatibility and that of thermal/chemical incompatibility. A typical ceramic chip decoupling capacitor may have dimensions on the order of a millimeter on a side, whereas the typical height of features on the integrated circuit is a few microns. This vast difference in sizes causes incompatibility with many packaging and interconnection standards. Similarly, a typical ceramic chip decoupling capacitor will not withstand a hydrofluoric acid etching step, or processing at high temperature, or other stressful processing steps encountered in the fabrication of an integrated circuit. Such steps can sometimes be avoided, but at the cost of flexibility in circuit design.
A potential compromise is to integrate decoupling capacitors in a dense multichip packaging scheme, such as multichip modules, wherein several integrated circuits are combined in a single package for improved operation. Again, however, decoupling capacitors based on conventional integrated circuit fabrication are impractical, owing to the enormous amount of surface area required. As many multichip packages are fabricated from ceramics using fairly conventional thin- and thick-film technologies for fabrication of the required interconnects between chips, it might seem that ceramic chip decoupling capacitors would be appropriate here.
Ceramic chip decoupling capacitors can be used in some multichip packaging applications, but are non-optimal. The most obvious problem is again related to relative size. The height of a typical ceramic chip decoupling capacitor is incompatible with many approaches toward wiring and encapsulating multichip modules. Also, ceramic chip decoupling capacitors are quite limited in their ability to withstand rapid large changes in temperature, owing to their multilayer construction (often as many as 100 fragile ceramic layers are contained in a ceramic chip decoupling capacitor, with those layers attached to metal sheets having very different thermal expansion). Thus, integrating ceramic chip decoupling capacitors into a ceramic structure which then needs to be fired and cured is fraught with danger of low production yield.
For the above and many other reasons, prior art approaches toward application of decoupling capacitors can usefully be improved. Note that, although the above discussion focuses on the use of capacitors in the role of decoupling noise from desired signals, such capacitors can also be used for signal coupling, filtering, impedance matching. Any application in which being able to add capacitance at a desired location on an integrated circuit chip or in a multichip package will benefit from development of improved capacitors and mounting techniques. Note further that the techniques herein developed to add capacitance at a desired location on an integrated circuit chip may also usefully comprise other circuit elements, such as resistors, inductors, and even active components (e.g., a high-frequency power transistor).
The point of the above discussion is that today's increased range of functionality of microelectronic circuitry requires new and improved approaches toward the integration of nF-range capacitors into integrated circuit packaging and interconnect technology. The desire for robust circuitry, less sensitive to increasingly noisy internal and working environments, is driving a clear need for improved capacitors and mounting techniques which are compatible with conventional microelectronic fabrication techniques.
The present invention relates generally to a new class of circuitry, termed applique circuits, and methods of fabricating and mounting them which address and aid in solving many of the problems outlined above. To continue use of the example of decoupling capacitors, the basic design principle is to fabricate thin-film decoupling capacitors comprising a dielectric (e.g., a ferroelectric material) with a very high (typically on the order of 1000) dielectric constant on a substrate, attaching these decoupling capacitors to a mechanical grip, etching away the substrate, thereby forming an applique circuit comprising a thin-film decoupling capacitor. In use, the applique circuit is bonded in the desired position on, e.g., an integrated circuit, and then the mechanical grip is removed, leaving the thin-film capacitor mounted on the integrated circuit.
Our thin-film decoupling capacitors are typically a few microns in height, and can supply perhaps 1000 nanoFarads per square centimeter, so both thickness and surface area become freely compatible with integration on the integrated circuit itself, where such elements can function most effectively. Although our decoupling capacitors can be applied in the final stages of integrated circuit fabrication for most applications, they are sufficiently robust to withstand most integrated circuit fabrication steps, and so, if necessary, can be added at earlier points in the fabrication process. They are also very suitable for use in multichip packaging applications, being small in size and robust under most ceramic processing conditions. Various embodiments and other features, aspects, and advantages of the present invention will become better understood with reference to the following description and appended claims.